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PD - 94637A
IRF8113
HEXFET(R) Power MOSFET
Applications l Synchronous MOSFET for Notebook Processor Power l Synchronous Rectifier MOSFET for
Isolated DC-DC Converters in Networking Systems Benefits l Very Low RDS(on) at 4.5V VGS l Low Gate Charge l Fully Characterized Avalanche Voltage and Current
VDSS
RDS(on) max
Qg Typ. 24nC
30V 5.6m:@VGS = 10V
S S S G
1
8
A A D D D D
2
7
3
6
4
5
Top View
SO-8
Absolute Maximum Ratings
Parameter
VDS VGS ID @ TA = 25C ID @ TA = 70C IDM PD @TA = 25C PD @TA = 70C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Power Dissipation
Max.
30 20 17.2 13.8 135 2.5 1.6 0.02 -55 to + 150
Units
V
f f
c
A W
Linear Derating Factor Operating Junction and Storage Temperature Range
W/C C
Thermal Resistance
RJL RJA
g Junction-to-Ambient fg
Junction-to-Drain Lead
Parameter
Typ.
--- ---
Max.
20 50
Units
C/W
Notes through are on page 10
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1
1/5/04
IRF8113
Static @ TJ = 25C (unless otherwise specified)
Parameter
BVDSS VDSS/TJ RDS(on) VGS(th) VGS(th) IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
30 --- --- --- 1.5 --- --- --- --- --- 73 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 0.024 4.7 5.8 --- - 5.4 --- --- --- --- --- 24 6.2 2.0 8.5 7.3 10.5 10 13 8.9 17 3.5 2910 600 250 --- --- 5.6 6.8 2.2 --- 1.0 150 100 -100 --- 36 --- --- --- --- --- --- --- --- --- --- --- --- --- pF VGS = 0V VDS = 15V ns nC nC VDS = 15V VGS = 4.5V ID = 13.3A S nA V mV/C A V m
Conditions
VGS = 0V, ID = 250A VGS = 10V, ID = 17.2A VGS = 4.5V, ID = 13.8A VDS = VGS, ID = 250A VDS = 24V, VGS = 0V VDS = 24V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V VDS = 15V, ID = 13.3A
V/C Reference to 25C, ID = 1mA
e e
See Fig. 16 VDS = 10V, VGS = 0V VDD = 15V, VGS = 4.5V ID = 13.3A Clamped Inductive Load
e
= 1.0MHz
Avalanche Characteristics
EAS IAR Parameter Single Pulse Avalanche Energy Avalanche Current
d
Typ. --- ---
Max. 48 13.3
Units mJ A
Diode Characteristics
Parameter
IS ISM VSD trr Qrr Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge
Min. Typ. Max. Units
--- --- --- --- --- --- --- --- 34 21 3.1 A 135 1.0 51 32 V ns nC
Conditions
MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, IS = 13.3A, VGS = 0V TJ = 25C, IF = 13.3A, VDD = 10V di/dt = 100A/s
e
e
2
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IRF8113
1000
VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V TOP
1000
ID, Drain-to-Source Current (A)
100
ID, Drain-to-Source Current (A)
100
VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V TOP
2.5V
10
10
2.5V 20s PULSE WIDTH Tj = 25C
1 0.01 0.1 1 10 100
20s PULSE WIDTH Tj = 150C
1 0.01 0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.0
100
RDS(on) , Drain-to-Source On Resistance
ID, Drain-to-Source Current ()
ID = 16.6A VGS = 10V
1.5
T J = 25C
10
(Normalized)
T J = 150C
1.0
1 2.5 3.0
VDS = 15V 20s PULSE WIDTH
3.5 4.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160
VGS , Gate-to-Source Voltage (V)
T J , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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3
IRF8113
100000
VGS , Gate-to-Source Voltage (V)
VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, C ds SHORTED Crss = Cgd Coss = Cds + Cgd
12 ID= 13.3A 10 8 6 4 2 0 VDS= 24V VDS= 15V
C, Capacitance (pF)
10000
Ciss
1000
Coss Crss
100 1 10 100
0
10
20
30
40
50
60
VDS, Drain-to-Source Voltage (V)
Q G Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000.0
1000 OPERATION IN THIS AREA LIMITED BY R DS(on)
100.0
T J = 150C 10.0
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
10
100sec 1msec
1.0
T J = 25C VGS = 0V
1 Tc = 25C Tj = 150C Single Pulse 0.1 1.0 10.0
10msec
0.1 0.2 0.4 0.6 0.8 1.0 1.2 VSD, Source-toDrain Voltage (V)
0.1
100.0
1000.0
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRF8113
18
2.2
VGS(th) Gate threshold Voltage (V)
16 14
2.0 1.8
ID , Drain Current (A)
12 10 8 6 4 2 0 25 50 75 100 125 150
ID = 250A
1.6 1.4 1.2 1.0 0.8 -75 -50 -25 0 25 50 75 100 125 150
T J , Junction Temperature (C)
T J , Temperature ( C )
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10. Threshold Voltage Vs. Temperature
100
Thermal Response ( Z thJA )
10
D = 0.50 0.20 0.10 0.05
1
0.02 0.01
J J 1
R1 R1 2
R2 R2
R3 R3 3
R4 R4 C 4
Ri (C/W)
0.924 13.395 22.046 14.911
i (sec)
0.000228 0.1728 1.5543 22.5
0.1
1
2
3
4
0.01
Ci= i/Ri Ci i/Ri
SINGLE PULSE ( THERMAL RESPONSE )
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthja + Tc
0.001 0.01 0.1 1 10 100
0.001 1E-006 1E-005 0.0001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
IRF8113
200
EAS, Single Pulse Avalanche Energy (mJ)
15V
160
VDS
L
DRIVER
ID 7.3A 8.2A BOTTOM 13.3A
TOP
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
120
A
0.01
80
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
40
0 25 50 75 100 125 150
Starting T J , Junction Temperature (C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
LD
I AS
VDS
Fig 12b. Unclamped Inductive Waveforms
+
VDD D.U.T
Current Regulator Same Type as D.U.T.
VGS Pulse Width < 1s Duty Factor < 0.1%
50K 12V .2F .3F
Fig 14a. Switching Time Test Circuit
D.U.T. + V - DS
VDS
90%
VGS
3mA
10%
IG ID
VGS
td(on) tr td(off) tf
Current Sampling Resistors
Fig 13. Gate Charge Test Circuit
Fig 14b. Switching Time Waveforms
6
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IRF8113
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
Id Vds Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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IRF8113
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by;
* P =P loss conduction + P drive + P output
P = Irms x Rds(on) loss
+ (Qg x Vg x f )
(
2
)
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
Q + oss x Vin x f + (Qrr x Vin x f ) 2
*dissipated primarily in Q1. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs' susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on.
Ploss = (Irms x Rds(on ) )
2
Qgs 2 Qgd +I x x Vin x f + I x x Vin x f ig ig + (Qg x Vg x f ) + Qoss x Vin x f 2
This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage.
Figure A: Qoss Characteristic
8
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IRF8113
SO-8 Package Details
D A 5 B
DIM A b INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00
A1 .0040
6 E
8
7
6
5 H 0.25 [.010] A
c D E e e1 H
1
2
3
4
.050 BASIC .025 BASIC .2284 .0099 .016 0 .2440 .0196 .050 8
1.27 BAS IC 0.635 BAS IC 5.80 0.25 0.40 0 6.20 0.50 1.27 8
6X
e
K L y
e1
A
K x 45 C 0.10 [.004] y 8X c
8X b 0.25 [.010]
A1 CAB
8X L 7
NOT ES : 1. DIMENS IONING & T OLERANCING PER AS ME Y14.5M-1994. 2. CONT ROLLING DIMENS ION: MILLIMET ER 3. DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ]. 4. OUT LINE CONFORMS T O JEDEC OUT LINE MS -012AA. 5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS . MOLD PROT RUS IONS NOT T O EXCEED 0.15 [.006]. 6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS . MOLD PROT RUS IONS NOT T O EXCEED 0.25 [.010]. 7 DIMENS ION IS THE LENGT H OF LEAD F OR S OLDERING T O A S UBS T RAT E. 3X 1.27 [.050] 6.46 [.255]
FOOT PRINT 8X 0.72 [.028]
8X 1.78 [.070]
SO-8 Part Marking
EXAMPLE: T HIS IS AN IRF7101 (MOSFET ) DAT E CODE (YWW) Y = LAS T DIGIT OF T HE YEAR WW = WEEK LOT CODE PART NUMBER
9
INT ERNATIONAL RECT IFIER LOGO
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YWW XXXX F7101
IRF8113
SO-8 Tape and Reel
TERMINAL NUMBER 1
12.3 ( .484 ) 11.7 ( .461 )
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES: 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00 (12.992) MAX.
14.40 ( .566 ) 12.40 ( .488 ) NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25C, L = 0.54mH RG = 25, IAS = 13.3A. Pulse width 400s; duty cycle 2%. When mounted on 1 inch square copper board R is measured at TJ approximately 90C
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.1/04
10
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